A. Field of the Invention
The invention relates generally to a method of manufacturing a silicon carbide semiconductor device (hereinafter referred to as a “SiC semiconductor device). Specifically, the present invention relates to a method of manufacturing a SiC semiconductor device having a MOS-type gate structure employing SiC for the semiconductor material thereof.
B. Description of the Related Art
The use of silicon carbide (hereinafter referred to as “SiC”) in power semiconductor devices has been investigated. The band gap of 4H-SiC is a very wide 3.25 eV, which is 3 times as wide as the band gap of silicon (hereinafter referred to as “Si”), which is 1.12 eV. Furthermore, the electric field strength in SiC is from 2 to 4 MV/cm, or about one order of magnitude higher than that in Si. It is known that the resistance of a semiconductor device in the ON-state thereof (hereinafter referred to as the “on-resistance”) is generally inversely proportional to the cube of the electric field strength and inversely proportional to the carrier mobility. Although the carrier mobility in SiC is lower than the carrier mobility in Si, the on-resistance of a SiC device can be reduced to several hundredths of the on-resistance of the Si device. Therefore, SiC devices have been expected to be power semiconductor devices for the next generation. Various SiC devices such as SiC diodes, SiC transistors, and SiC thyristors have been fabricated experimentally. These SiC devices include MOS field effect transistors having a MOS-type gate structure (hereinafter referred to as “MOSFETs”). The MOSFETs further include double-implanted MOSFETs (hereinafter referred to as “DIMOSFETs”) having a double-diffused channel structure and UMOSFETs, having a gate structure that includes a gate buried in a U-shaped trench.
FIG. 15 is a cross sectional view of a conventional vertical DIMOSFET using SiC. FIG. 15 shows the cross section of one cell in the SiC n-channel DIMOSFET. Referring now to FIG. 15, SiC vertical DIMOSFET 100 includes n-type SiC substrate 101 exhibiting low electrical resistance and n-type drift layer 102 formed on n-type SiC substrate 101 by the epitaxial growth of a SiC layer. P-type base region 103 is formed by implanting aluminum ions (hereinafter referred to as “Al ions”) and such p-type impurity ions into the surface portion of n-type drift layer 102. N-type source region 104 is formed by implanting nitrogen ions (hereinafter referred to as “N ions”) or phosphorus ions (hereinafter referred to as “P ions”) into the surface portion of p-type base region 103 such that n-type source region 104 is surrounded by p-type base region 103. Gate oxide film 105 is formed on the semiconductor structure formed so far and polysilicon gate electrode 106 is formed on gate oxide film 105. Gate electrode 106 is covered with insulator film 107. Source electrode 108 contacting commonly with p-type base region 103 and n-type source region 104 is formed on p-type base region 103 and n-type source region 104. Drain electrode 109 is formed on the back surface of n-type SiC substrate 101.
In SiC vertical DIMOSFET 100, the sandwiched portion of p-type base region 103, sandwiched between n-type source region 104 and n-type drift layer 102 beneath gate electrode 106, works as channel region 110. To improve the characteristics of the MOSFET, it is important to control the lengths L1 of channel regions 110 to be identical between the cells in the ion implantation steps for forming p-type base regions 103 and n-type source regions 104. A method of forming channel regions 110 with the lengths thereof controlled has been proposed (cf. JP P2000-22137A, paragraphs [0035] through [0044] and FIGS. 1 and 2).
When a sufficiently large negative bias voltage is applied to gate electrode 106 in the OFF-state in which source electrode 108 has been biased at the ground potential, the SiC vertical DIMOSFET is in accumulation mode, in which holes are induced in channel region 110 and no current flows. Since the junction between n-type drift layer 102 and p-type base region 103 is biased in reverse when a positive high voltage is applied to drain electrode 109, depletion layers expand into n-type drift layer 102 and p-type base region 103 and a high voltage is sustained while the current is suppressed at a low value, resulting in the OFF-state of the device. When a sufficiently high positive bias voltage is applied to gate electrode 106 in the OFF-state of the device, the SiC vertical DIMOSFET is in inversion mode, in which electrons are induced in channel region 110 and electrons flow from source electrode 108 to drain electrode 109 via n-type source region 104, channel region 110 (inversion layer), n-type drift layer 102, and n-type SiC substrate 101. This results in the ON-state of the device. When a negative bias voltage is applied again to gate electrode 106 in the ON-state of the device, the inversion layers vanish and the current paths are interrupted, resulting in the OFF-state of the device.
The on-resistance of SiC vertical DIMOSFET 100 is the sum of the resistance components. The resistance components include the contact resistance of source electrode 108, the source resistance, the channel resistance of the inversion layer, the accumulation resistance caused against the electron movement in the vicinity of the boundary between n-type drift layer 102 and gate oxide film 105, the JFET resistance caused against the electron flow in the portion of n-type drift layer 102, sandwiched between p-type base regions 103, from the vicinity of gate oxide film 105 toward n-type SiC substrate 101, the resistance of n-type drift layer 102 in the thickness direction thereof excluding p-type base regions 103, the substrate resistance, and the contact resistance of drain electrode 109.
SiC vertical DIMOSFET 100 exhibits the following advantages. First, since any built-in voltage is not caused in SiC vertical DIMOSFET 100, theoretically the on-resistance of SiC vertical DIMOSFET 100 is lower than the on-resistance of the bipolar devices. Second, since SiC vertical DIMOSFET 100 is a unipolar device, carrier accumulation does not occur in the ON-state thereof and therefore the switching loss thereof is low. Third, since SiC vertical DIMOSFET 100 is a voltage-driven-type device, the ON-OFF operations thereof are conducted by applying positive and negative voltages to the gate electrode and the driving circuit for driving SiC vertical DIMOSFET 100 is simple.
FIG. 16 is a cross sectional view of a conventional vertical UMOSFET using SiC. FIG. 16 shows the cross section of one cell in the SiC n-channel UMOSFET. Referring now to FIG. 16, SiC vertical UMOSFET 200 includes, in the same manner as SiC vertical DIMOSFET 100 does, n-type SiC substrate 201 which exhibits low electrical resistance and n-type drift layer 202 formed on n-type SiC substrate 201 by the epitaxial growth of a SiC layer. P-type base region 203 is formed on n-type drift layer 202 by the epitaxial growth of a SiC layer. N-type source region 204 is formed by implanting N ions or P ions into the surface portion of p-type base region 203. Then, a trench is etched down to n-type drift layer 202 by reactive ion etching (hereinafter referred to as “RIE”). Gate oxide film 205, gate electrode 206 and insulator layer 207 are formed such that gate oxide film 205, gate electrode 206 and insulator layer 207 cover the trench. Source electrode 208 contacting commonly with p-type base region 203 and n-type source region 204 is formed on p-type base region 203 and n-type source region 204. Drain electrode 209 is formed on the back surface of n-type SiC substrate 201. In SiC vertical UMOSFET 200, the portion of p-type base region 203 between n-type source region 204 and n-type drift layer 202 serves as channel region 210.
SiC vertical UMOSFET 200 conducts ON-OFF operations in the same manner as SiC vertical DIMOSFET 100. However, the accumulation resistance and the JFET resistance, which are caused in SiC vertical DIMOSFET 100, are not caused in SiC vertical UMOSFET 200. Since no JFET resistance is caused, the distance between adjacent p-type base regions 203 and 203 can be shortened and, therefore, the cell pitch can be shortened. Since the cell pitch can be shortened, the on-resistance of SiC vertical UMOSFET 200 can be set to be lower than the on-resistance of SiC vertical DIMOSFET 100.
Various proposals have been made for improving the characteristics of conventional SiC semiconductor devices. For example, the boundary between the channel region and the gate insulator film is brought into a good shape by interposing a buffer layer formed by the thermal oxidation of SiC between the SiC channel region and the gate insulator film to prevent carrier trapping and carrier scattering so that the carrier mobility may be improved (cf. JP P2002-222950A, Paragraphs [0045] through [0047] and FIG. 4). The carrier mobility also is improved by doping carbon into the Si channel layer, which exerts tensile stress to the channel region and improves the carrier mobility (cf. JP PHei.8 (1996)-111528A, Paragraphs [0014] through [0017] and FIGS. 1 and 2).
As the breakdown voltage of the SiC semiconductor device is set to be higher, the resistance of the drift layer rises as described in the following formula (1):Rdrift=4BV2/(μεECR3)  (1)
Here, BV represents the dielectric breakdown voltage, μ represents the carrier mobility, ε represents the dielectric permeability of the semiconductor, and ECR represents the critical electric field strength of the semiconductor. The Rdrift described by the formula (1) is the minimum on-resistance of the unipolar device. The on-resistance related by the formula (1) with the dielectric breakdown voltage is called a “unipolar limit,” which indicates the theoretical lower limit value of the on-resistance.
However, various resistance components are caused in SiC semiconductor device in addition to the drift layer resistance. Due to the additional resistance components, the real on-resistance is far from the unipolar limit. As the dielectric breakdown voltage is lower, the ratios of the other resistance components to the drift layer resistance become higher.
In the MOSFET for example, the channel resistance described in the following formula (2) occupies a large part.RCH=L/{WCOXμn (VG−VT)}  (2)
Here, L represents the channel length, W the channel width, COX the oxide film capacitance, μn the electron mobility, VG the gate voltage, and VT the threshold gate voltage.
In the JFET, JFET resistance is caused when the length of the drift layer sandwiched by the gate regions is short. Although the JFET resistance may be set to be negligible by elongating the length of the drift layer sandwiched by the gate regions, the resistance component caused against the electrons flowing through the deep portions of the gate regions and described in the following formula (3) is added to the total resistance.R=LJFET/(q μnn)·(Ratio)  (3)
Here, LJFET represents the depth of the gate region, q the charge quantity, μn the electron mobility, n the electron density in the drift layer, and (Ratio) the ratio of the area of the drift layer in each cell sandwiched by the gate regions to the total area of each cell.
Although various resistance components contribute to the on-resistance, the resistance values of the MOSFET and the JFET are affected greatly by the electron mobility μn. In the JFET, the electron mobility μn is the electron mobility in the bulk. In the MOSFET, the electron mobility gun is lower than the electron mobility in the bulk, since the number of the electrons is reduced by the trapping thereof by the trap levels existing in the boundary between SiC and the gate oxide film and Coulomb scattering is caused by the trapped electrons. To obviate this problem, the boundary levels are lowered or the channel is spaced apart from the boundary to minimize the influence of the boundary levels. One target is to make the electron mobility μn closer to the electron mobility in the bulk as much as possible. Although the electron mobility μn may be made to be closer to the electron mobility in the bulk, the channel resistance still occupies a large part of the drift layer resistance at a low breakdown voltage lower than 1 kV.
In view of the foregoing, it would be desirable to obviate the problems described above. It would also be desirable to provide a method of manufacturing a SiC semiconductor device that facilitates greatly improving the carrier mobility in the device and greatly reducing the on-resistance even at a low breakdown voltage. The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.